RISC-V: Accelerating
Next-Generation Computing
Architectures

Supporting the RISC-V Ecosystem


RISC-V is an open ISA enabling a new era of processor innovation. To further accelerate open standard interfaces and RISC-V processing architectures, Western Digital offers three open-source innovations designed to support both internal RISC-V development efforts as well as those of the growing RISC-V ecosystem.

New SweRV Core 1.1 and SweRV ISS

The Western Digital SweRV Core™ EHX1 is a 32-bit, 2-way superscalar, 9 stage pipeline core. The SweRV Core version 1.1 is the newest release, featuring performance enhancements, bug fixes and improved trace/debug capabilities. With an expected simulation performance of up to 5.0 CoreMarks/Mhz 1 and small footprint, it offers compelling capabilities for embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. The power-efficient design also offers clock speeds of up to 1.8Ghz 1 on a 28nm CMOS process technology. The SweRV Core will be used in Western Digital products in the coming years. The SweRV Core 1.1 is now open sourced for the RISC-V community to utilize and contribute to.

risc-v-swerve-core-flow-western-digital

SweRV ISS™ (Instruction Set Simulator) is also available with full test bench support for validation of RISC-V cores. This open-source ISS was developed independently from the SweRV Core to ensure RISC-V cores are executing instructions properly. The SweRV ISS models closely coupled memories, caches, interrupts and more. It was used to rigorously simulate and validate the SweRV Core, with more than 10 billion instructions executed.

swerve_risc-v_chart_western_digital
Video

Strategic Innovation: RISC-V at Western Digital

OmniXtend

OmniXtend™ enables innovations in data center architectures, purpose built compute acceleration and CPU microarchitecture

Eathernet Fabric Risc-V WesternDigital

OmniXtend™ is a new open approach to providing cache coherent memory over an ethernet fabric. This memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components. It is a truly open solution for efficiently attaching persistent memory to processors and offers potential support of future advanced fabrics that connect compute, storage, memory and I/O components.

OmniXtend Implementation Risc-V WesternDigital

OmniXtend is made possible by leveraging the configurability and open nature of RISC-V. It starts with an open cache coherency bus, which is available with RISC-V. Then an implementation which serializes this bus and transports it over Ethernet enables a fabric to be possible. Western Digital partnered with Barefoot Networks and have run OmniXtend thorough a Tofino switch.

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Innovating for a Data-Centric World

Press Release

Western Digial Extends Openness of PlatformIO and Enhances Its RISC-V Portfolio to Accelerate Data-Centric Innovation

Apr 4, 2019

Western Digital Corp. (NASDAQ: WDC) today announced a new a strategic partnership with PlatformIO Labs, OÜ, in collaboration with SiFive, Inc., to extend...

RISC-V Foundation

Event

RISC-V Events

Apr 4, 2019

The RISC-V Foundation regularly conducts events and workshops. Participate in an event near you.

OmniXtend Cache Coherent Fabric

Video

Datacenter Processors with OmniXtend Interfaces for Shared Memory and AI Workload Acceleration

March 13, 2019

Presentation by Paul Loewenstein at Western Digital on March 13, 2019 at the RISC-V Workshop Taiwan, at the Ambassador Hotel in Hsinchu City, Taiwan.

RISC-V based NAS

Video

WDC RISC-V Summit 2018 | Atish Patra

Feb 1, 2019

A RISC-V based Network Attached Storage (NAS); See a demo of a Linux capable, RISC-V based NAS demo using a SMR drive. This is a full open sourced project.

OmniXtend Cache Coherent Fabric video

Video

WDC RISC-V Summit 2018 | Dejan Vucinic

Feb 1, 2019

An open cache coherent fabric, OmniXtend; See how RISC-V enables an open solution for scaling cache coherency over an Ethernet fabric.

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Disclosures

1. Based on Internal Testing