RISC-V Summit 2020
A Virtual Event
December 08, 2020 - December 10, 2020
ABOUT THE EVENT
COLLABORATE. INNOVATE. BUILD IT.
RISC-V Summit is going virtual! Join us online December 8-10
Your chance to network with thought-leaders, technology companies, and researchers spearheading the adoption of this transformative change in the silicon market. Secure your virtual seat!
Speaking Engagements
Topic
Details
KEYNOTE SESSIONS
Date: December 08th, 2020
Speaker Name: Siva Sivaram
Speaker Title: President, Technology and Strateg
Time: 9:15AM
Session Name: RISC-V and Chips Alliance Address new Compute Requirements
Speaker Name: Siva Sivaram
Speaker Title: President, Technology and Strateg
Time: 9:15AM
Session Name: RISC-V and Chips Alliance Address new Compute Requirements
BREAKOUTS
Date: December 8th, 2020
Speaker Name: Atish Patra
Speaker Title: Technologist & Tu Dang – Technologist
Time: 3:30PM – 3:50PM
Session Name: Building Cache-coherent Scaleout Systems with Ominxtend
Speaker Name: Atish Patra
Speaker Title: Technologist & Tu Dang – Technologist
Time: 3:30PM – 3:50PM
Session Name: Building Cache-coherent Scaleout Systems with Ominxtend
Date: December 9th, 2020
Speaker Name: Alistair Francis
Speaker Title: Technologist, R&D Engineering
Time: 3:30PM – 3:50PM
Session Name: Porting Tock to OpenTitan
Speaker Name: Alistair Francis
Speaker Title: Technologist, R&D Engineering
Time: 3:30PM – 3:50PM
Session Name: Porting Tock to OpenTitan
Date: December 9th, 2020
Speaker Name: Zvominir Bandic
Speaker Title: Sr. Director, Next Gen Platform Technologies
Time: 12:30PM – 12:50PM
Session Name: OmniXtend: Open Source Cache-coherent over Ethernet
Speaker Name: Zvominir Bandic
Speaker Title: Sr. Director, Next Gen Platform Technologies
Time: 12:30PM – 12:50PM
Session Name: OmniXtend: Open Source Cache-coherent over Ethernet