Addressing Next-Generation Compute Requirements
The open source model, proven by the success of Linux®, now has a hardware platform in RISC-V to enable the next generation of innovation. Another reason is that the configurability RISC-V provides is unparalleled. By leveraging the open collaboration and flexibility of RISC-V, Western Digital can create processors that are purpose-built for data-centric applications.
Download a summary of the RISC-V initiatives Western Digital has invested in.
RISC-V is more than a processor ISA. The open nature of the specification enables new compute architectures such as OmniXtend.
Western Digital 2020 RISC-V Summit Keynote discussing next generation storage and compute. Siva Sivaram discusses Western Digital’s first RISC-V SweRV Core SoC in a prototype SSD. Updates to the SweRV Core family and an invitation to collaborate on a unified memory standard for heterogeneous processing.
Technical details on Western Digital’s new RISC-V SweRV Core EH2 and EL2.
The RISC-V open ISA has enabled a new generation of processing architectures. There now exists an open hardware group, CHIPS Alliance where organizations, non-profits, individuals, and academia can collaborate to solve the next generation of processing challenges. See the milestones that CHIPS Alliance has already accomplished and learn about our roadmap and future vision for open source hardware.
CHIPS Alliance keynote at the 2019 RISC-V Summit explaining the organization and the latest development efforts.
A detailed video explaining how to set up an OmniXtend demo. This demo uses two FPGA boards and a programmable Ethernet switch. It explains the programming of the FPGA boards and the P4 code needed to run on the switch.
OmniXtend has become the de facto standard for building multi-socket RISC-V systems. Recent efforts within the Interconnects Workgroup in CHIPS Alliance resulted in the definition of an initialization and configuration protocol which enables the construction of massively parallel systems of arbitrary size.
Technical update on OmniXtend, a cache coherent Ethernet based memory fabric.
This talk will cover the Y2038 Unix Epoch overflow problem and what is being done to fix it. It will describe how and why this applies to the 32-bit RISC-V glibc port.
The latest GCC code density improvements for RISC-V.
Technical update on QEMU and hypervisor support for RISC-V.
Forward Looking Statements
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1. Source: Market Trends: Custom ICs Based on RISC-V Will Enable Cost-Effective IoT Product Differentiation by Amy Teng (Gartner, 6/5/2020)
2. Source: The Journey of RISC-V Implementation by Ted Marena (AllAboutCircuits.com, 9/10/2019)
3. Source: WD Rolls its own RISC-V Core (Microprocessor report, 2/4/2019).
4. Source: How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation by Ted Marena (AllAboutCircuits.com, 3/20/2019).
5. Source: CHIP Alliance’s Newly Enhanced SweRV Cores Available to All for Free (CHIP Alliance, 5/14/2020)