Addressing Next-Generation Compute Requirements

Unleashing the power of data through RISC-V initiatives

The open source model, proven by the success of Linux®, now has a hardware platform in RISC-V to enable the next generation of innovation. Another reason is that the configurability RISC-V provides is unparalleled. By leveraging the open collaboration and flexibility of RISC-V, Western Digital can create processors that are purpose-built for data-centric applications.

RISC-V is an open ISA enabling a new era of processor innovation.

Featured Videos


Strategic Innovation: RISC-V at Western Digital


RISC-V 2020 Summit: The March of RISC-V

Western Digital 2020 RISC-V Summit Keynote discussing next generation storage and compute. Siva Sivaram discusses Western Digital’s first RISC-V SweRV Core SoC in a prototype SSD. Updates to the SweRV Core family and an invitation to collaborate on a unified memory standard for heterogeneous processing.


RISC-V SweRV Core Family Overview


RISC-V Summit 2019: SweRV Cores Roadmap

Technical details on Western Digital’s new RISC-V SweRV Core EH2 and EL2.


RISC-V Summit 2020: The Open Source Hardware Roadmap - Zvonimir Bandic, Chairman, CHIPS Alliance

The RISC-V open ISA has enabled a new generation of processing architectures. There now exists an open hardware group, CHIPS Alliance where organizations, non-profits, individuals, and academia can collaborate to solve the next generation of processing challenges. See the milestones that CHIPS Alliance has already accomplished and learn about our roadmap and future vision for open source hardware.


RISC-V Summit 2019: RISC-V and Chips Alliance Address new Compute Requirements

CHIPS Alliance keynote at the 2019 RISC-V Summit explaining the organization and the latest development efforts.


How to set up OmniXtend coherent memory fabric demo with RISC-V and Tofino

A detailed video explaining how to set up an OmniXtend demo. This demo uses two FPGA boards and a programmable Ethernet switch. It explains the programming of the FPGA boards and the P4 code needed to run on the switch.


RISC-V Summit 2020: Omnixtend Boot Protocol and Coherent Scaleout - Dejan Vucinic, Western Digital Corporation

OmniXtend has become the de facto standard for building multi-socket RISC-V systems. Recent efforts within the Interconnects Workgroup in CHIPS Alliance resulted in the definition of an initialization and configuration protocol which enables the construction of massively parallel systems of arbitrary size.


RISC-V Summit 2019: An Open and Coherent Memory Centric Architecture Enabled by RISC-V

Technical update on OmniXtend, a cache coherent Ethernet based memory fabric.


RISC-V Summit 2020: Where Is the 32-Bit Glibc Port? - Alistair Francis, Western Digital

This talk will cover the Y2038 Unix Epoch overflow problem and what is being done to fix it. It will describe how and why this applies to the 32-bit RISC-V glibc port.


RISC-V Summit 2019: Headline Sponsor Western Digital presents GCC Compiler Code Size Density

The latest GCC code density improvements for RISC-V.


RISC-V Summit 2019: Headline Sponsor Western Digital presents RISC V Hypervisor Support

Technical update on QEMU and hypervisor support for RISC-V.

Forward Looking Statements
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1. Source: Market Trends: Custom ICs Based on RISC-V Will Enable Cost-Effective IoT Product Differentiation by Amy Teng (Gartner, 6/5/2020)
2. Source: The Journey of RISC-V Implementation by Ted Marena (AllAboutCircuits.com, 9/10/2019)
3. Source: WD Rolls its own RISC-V Core (Microprocessor report, 2/4/2019).
4. Source: How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation by Ted Marena (AllAboutCircuits.com, 3/20/2019).
5. Source: CHIP Alliance’s Newly Enhanced SweRV Cores Available to All for Free (CHIP Alliance, 5/14/2020)